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    • 专利摘要:
    The invention relates to a method for producing a crystalline layer from a crystalline substrate (100) of a first material on which a masking layer (200) has previously been deposited; said masking layer (200) comprising at least one trench forming an access to the substrate (100), characterized in that the trench has a depth at least equal to a value Hc such that Hc = KStan (0) where K is at less than 0.7, S is the width of the trench and 0 is the angle of the dislocations relative to the plane of the substrate (100) and in that the method comprises the following steps: - formation of a crystalline buffer layer (300) at least partially in the trench of the masking layer (200), extending from the substrate (100) and protruding beyond the masking layer (200) so that an upper portion of side flanks of said buffer layer (300) is left uncovered, the forming step comprising growing the buffer layer (300) from the substrate (100) so as to give the buffer layer (300) the crystal structure of the crystalline substrate (100), - formation of an epic layer axial axis (500) crystallizes into a second material, different from the material of the buffer layer (300), by growing from said upper portion of the lateral flanks of the buffer layer (300) left uncovered.
    公开号:FR3023058A1
    申请号:FR1456201
    申请日:2014-06-30
    公开日:2016-01-01
    发明作者:Emmanuel Augendre；Thierry Baron
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] FIELD OF THE INVENTION The present invention relates to devices for microelectronics and their methods of realization. It relates in particular to semiconductors having high mobility (for example, based on carbon, germanium, alloys of Group III-V elements, or constrained silicon), which are considered as alternative to silicon for certain applications in the nodes. ultimate technologies. TECHNOLOGICAL BACKGROUND In the field of microelectronics, the constant decrease in the silicon surface occupied by the components has so far made it possible to maintain the race for integration at a rate prescribed by Moore's Law, which provides that the number of transistors per integrated circuit doubles every 18 to 24 months. However, this integration race is about to meet the physical and technological limits that the transistor of the Metal-Oxide-Semiconductor ("MOS") type on solid silicon will obviously not be able to overcome. In addition, the solid silicon architecture will not be able to contain, beyond a certain integration threshold, two-dimensional electrostatic forces and certain quantum effects detrimental to the vertical field effect induced by the grid. Current research in microelectronics is exploring new component architectures, alternatives to the conventional "MOS" transistor. In addition, the development of innovative thin-silicon architectures in combination with other so-called "exotic" materials with high mobility (for example, based on carbon, germanium, alloys of group III elements -V) could allow to continue the race to the miniaturization of the components of type "CMOS" (acronym for "Complementary Metal Oxide Semiconductor"). Devices made on semiconductor-type materials other than silicon are most often obtained from epitaxial layers on massive substrates other than silicon (whose diameter is generally less than or equal to 200 millimeters). These bulk substrates other than silicon have the drawbacks of their cost and incompatibility in size with the equipment developed for the latest generations of silicon components (300 millimeters, 450 millimeters in preparation). The use of a solid silicon substrate thus remains the least expensive solution and the most compatible with the known manufacturing processes.
    [0002] To overcome these problems, the way has emerged to obtain these materials by epitaxial growth on a silicon host substrate of the desired size. However, this approach comes up against the strong disparity of mesh parameter between the main materials of interest and the silicon. For example, a difference in mesh parameters close to 4% is observed for germanium (Ge) and gallium arsenide (GaAs); this difference is about 8% for indium phosphide (InP). Under these conditions, obtaining a continuous epitaxial layer (over the entire host substrate), with a minimum of crystalline defects, requires the use of thick intermediate buffer layers, making the approach particularly expensive without being completely effective. Indeed, there is still a significant density of dislocations. By renouncing the obtaining of a continuous layer, it is possible to achieve lower dislocation densities for heteroepitaxied layers on a silicon substrate. This principle is known as "aspect ratio trapping" or "dislocation necking" which could be translated into French as "trapping by form ratio". Nevertheless, this approach has several limitations. These disadvantages are, for example, illustrated in FIGS. 1a to 1c, from the publication of J.-S. Park et al., Applied Physics Letter 90, 052113 (2007). FIG. 1a illustrates a schematic representation of the principle of dislocation confinement 50 of a germanium layer 300 formed from a substrate 100 of silicon (Si) inside a trench 250 formed in a masking layer 200 based on silicon oxide (SiO 2). The growth of the germanium layer 300 is in the trench 250 formed in a masking layer 200 which covers the silicon substrate 100. Due to a minimum shape ratio, the dislocations 50 are trapped on the flanks and the bottom. the layer 300, giving a material of better surface quality than the equivalent in continuous layer (for the same thickness). As shown in FIG. 1a, the transverse dislocations of the germanium layer 300 require that the masking layer 200 have a thickness greater than the width of the trenches 250. In addition, one of the major disadvantages is the emergence of dislocations 50 which is locked only in the high aspect ratio directions i.e. in a transverse direction of the trenches 250 (see Fig. 1b illustrating a cross-sectional view, obtained by transmission electron microscopy, " TEM ") but not in length (see FIG. 1c illustrating a view from above, obtained by transmission electron microscopy," TEM "). The dislocations 50 are represented by a more accentuated color contrast on the TEM images. It is thus seen that the crystalline defects (or dislocations 50), generated by the growth of the layer 300 from the substrate 100, are localized in the bottom of the trench 250, or at the interface with the substrate 100, and along Flasks of the masking layer 200. The strong mesh parameter mismatch between the substrate 100 and the layer 300 generates flaws, more commonly referred to as interface dislocations. Deformation of the crystal mesh in the upper layer changes the inclination angle of the crystal planes of said upper layer relative to the crystalline planes of the lower layer, forming an angle θ.
    [0003] On the other hand, it may be advantageous to grow a constrained material (that is, whose mesh parameter in a given direction is different from the relaxed mesh parameter). In this case, there is a limit called "critical thickness" beyond which the growth of the material can be accompanied by the creation of crystalline defects and relaxation of the stress. If it is desired to create constrained channels of "fine" type in a material obtained by vertical growth, the height of the "fine" channels is limited by this "critical thickness". In addition, obtaining dense patterns of the germanium layer 300 is directly limited by the minimum photo-repeat step. On the other hand, a further disadvantage lies in the width of the epitaxial channel formed by the layer 300 of germanium which directly undergoes the variations imposed by the trench formation steps 250; said trenches 250 being made by photolithography and / or etching, for example.
    [0004] An object of the present invention is thus to provide a method for producing at least one crystalline structure which limits, or even eliminates, at least some of the previously mentioned problems and disadvantages concerning known solutions of current techniques. More particularly, the object of the invention is to form a crystalline structure, for example intended to form a transistor channel, of a material other than that of the substrate, devoid of or having few crystalline defects.
    [0005] SUMMARY OF THE INVENTION The invention relates to a process for producing a crystalline layer from a crystalline substrate in a first material on which a masking layer has been previously deposited; said masking layer comprising at least one trench forming an access to the substrate.
    [0006] Advantageously, the trench has a depth at least equal to a value Hc such that Hc = KStan (0) where K is at least greater than 0.7, S is the width of the trench and 0 is the angle of the dislocations with respect to plane of the substrate.
    [0007] The method according to the invention comprises the following steps: - formation of a crystalline buffer layer located at least partially in the trench of the masking layer, extending from the substrate and projecting beyond the masking layer so that an upper portion of the side flanks of said buffer layer is left exposed, the forming step comprising growing the buffer layer preferably by growth from the crystalline substrate so as to give the buffer layer a crystalline structure, - forming a crystalline epitaxial layer in a second material, different from the material of the buffer layer, by growth from said upper part of the lateral flanks of the buffer layer left uncovered. Thus, the present invention makes it possible in a simple and reproducible manner, from a crystalline substrate formed of a first material, at least one crystalline epitaxial layer to a second material which is advantageously different from the first material of the substrate. The invention makes it possible to trap the dislocations and other crystalline defects in the lower part of the buffer layer. The upper part of the latter which protrudes beyond the masking layer is thus free of dislocations and other crystalline defects on its lateral flanks. This upper part then serves as a basis for the growth of the crystalline epitaxial layer, also free of dislocations and other crystalline defects, which can cause malfunctions in a microelectronic device. The invention also makes it possible to form stressed epitaxial layers during the lateral growth phase, the vertical dimension of which exceeds the critical growth thickness, thanks to the fact that the last growth takes place laterally and not vertically (FIG. critical thickness being measured laterally rather than vertically). The crystalline epitaxial layer thus formed is for example intended to form a channel.
    [0008] The invention thus provides a simple, accurate and efficient solution for forming crystalline layers in a given material from a crystalline bulk substrate made of a different material. The invention also relates to a microelectronic device comprising a crystalline substrate covered with a masking layer comprising at least one trench forming an access to the substrate, the trench having a depth at least equal to its width, characterized in that it comprises: a crystalline buffer layer formed at least in part in the trench and extending from the substrate to protrude from the masking layer; - A crystalline epitaxial layer formed at least on a portion of the side flanks of the buffer layer which protrudes beyond the masking layer.
    [0009] Thus, a device is produced according to a method which, in a particularly advantageous manner, is not subject to the limitations encountered on the solid substrates, and in particular to the choice of the material and the aspect ratio. Optionally, the material of the epitaxial layer is selected so as to be able to grow on the material of the buffer layer. Optionally, the material of the buffer layer is chosen according to the orientation of the crystalline planes of the substrate. Optionally, at least some or each epitaxial layer form a channel of a transistor.
    [0010] BRIEF INTRODUCTION OF THE FIGURES Other characteristics, objects and advantages of the present invention will appear on reading the detailed description which follows, with reference to the appended drawings, given by way of nonlimiting examples, and in which: FIG. 1a illustrates a schematic representation of the dislocation confinement principle of a germanium layer formed from a silicon substrate within a silicon oxide trench. FIGURE 1b illustrates a cross-sectional view, obtained by transmission electron microscopy, of the dislocation confinement principle of a germanium layer formed from a silicon substrate within a trench-based of silicon oxide. FIG. 1c illustrates a view from above, obtained by transmission electron microscopy, of the dislocation confinement principle of a germanium layer formed from a silicon substrate inside an oxide-based trench of silicon. FIGS. 2a to 2f illustrate the formation of a crystalline layer according to a first embodiment of the invention. More specifically: FIGURE 2a illustrates the formation of a masking layer on the substrate; said masking layer comprising a plurality of layers.
    [0011] FIGURE 2b illustrates the formation of a trench in the masking layer so as to form an access opening in the substrate. FIGURE 2c illustrates the formation of a buffer layer in the trench of the masking layer.
    [0012] FIGURE 2d illustrates the formation of a protective layer at least on the upper face of the buffer layer. FIGURE 2e illustrates the partial selective removal of the masking layer so that the buffer layer protrudes beyond the masking layer, leaving at least the top face and part of the side flanks of the layer exposed. buffer. FIG. 2f illustrates the formation of the epitaxial layer on at least the part of the lateral flanks of the buffer layer left uncovered. FIGS. 3a to 3f illustrate the formation of a crystalline layer according to a second embodiment of the invention. More specifically: FIGURE 3a illustrates the formation of a masking layer on a substrate. FIGURE 3b illustrates the formation of a trench in the masking layer so as to form an access opening in the substrate. FIGURE 3c illustrates the formation of a buffer layer in the trench 20 of the masking layer. FIGURE 3d illustrates the formation of a protective layer on the layers. FIGURE 3e illustrates the partial removal of the protective layer so as to discover the side flanks of the buffer layer. FIGURE 3f illustrates the formation of the epitaxial layer on at least part of the side flanks of the buffer layer left uncovered. FIGURES 4a and 4b respectively illustrate a front view and a side view of a device comprising a finFET type transistor made from an epitaxial layer formed according to the method of the invention. The drawings are given by way of example and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily at the scale of practical applications. In particular, the relative thicknesses of the different layers are not representative of reality. It is specified that in the context of the present invention, the term "on" does not necessarily mean "in contact with". Thus, for example, the formation of a layer on another layer does not necessarily mean that the two layers are directly in contact with each other but that means that one of the layers at least partially covers the other being either directly in contact with it, or being separated from it by a film, another layer or another element. DETAILED DESCRIPTION Before proceeding to a detailed review of embodiments of the invention, are set forth below optional features that may optionally be used in combination or alternatively. It is recalled first of all that the invention relates to a method for producing a crystalline layer from a crystalline substrate. Preferentially, the growth of the buffer layer comprises an epitaxial growth from the substrate. Particularly advantageously, the epitaxial growth makes it possible to obtain a layer whose material is of better crystalline quality, thereby comprising a reduced number of dislocations. The epitaxial growth techniques are preferably chosen from chemical vapor deposition (CVD) or molecular beam epitaxy (MBE) techniques. "); these techniques are commonly used in industry. According to an alternative, the growth of the buffer layer comprises a deposition of said layer, followed by a crystallization annealing. For this type of deposit, the chemical vapor deposition can advantageously be used.
    [0013] In general, the crystalline buffer layer is grown from the seed crystal seed. Thus, said step of forming the buffer layer comprises growing the buffer layer by using the seed of the crystalline substrate as seed. The use of the crystal substrate seed allows to give the buffer layer a crystal structure that may be the same or different from that of the substrate. Advantageously, the masking layer, in particular its material and its structure, is chosen so as to prevent the growth of the epitaxial layer from the masking layer. This advantageously allows selective growth of the different layers. According to one embodiment, the formation of the buffer layer is carried out so as to leave exposed an upper face of the buffer layer in addition to said upper part of the lateral flanks of the buffer layer and, prior to the formation of the epitaxial layer. a protective layer is formed on said upper side of the buffer layer so that only said upper part of the lateral flanks of the buffer layer left exposed is exposed. Advantageously, the protective layer allows selective growth only on the lateral flanks of the buffer layer. Thus, the protective layer prevents epitaxial growth from the top of the buffer layer. This epitaxial growth is thus carried out only laterally from the flanks of the buffer layer.
    [0014] Preferably, the protective layer, in particular its material and its structure, is chosen so as to prevent the growth of the epitaxial layer from the protective layer. Particularly advantageously, the formation of the epitaxial layer comprises epitaxial growth from the upper side flanks of the buffer layer left uncovered. The epitaxial growth advantageously makes it possible to form a layer of good crystalline quality having a low density of dislocations. According to one embodiment, the formation of the epitaxial layer comprises anisotropic growth directed perpendicular to the lateral flanks of the buffer layer left uncovered. Advantageously, this anisotropic growth makes it possible to form channels of small width and having a low density of dislocations and other crystalline defects.
    [0015] According to another embodiment, the formation of the epitaxial layer comprises a deposit of amorphous material followed by a step of crystallization of said material. Advantageously, this embodiment is used for the formation of epitaxial layers comprising only elements of the column IV of the periodic table of possible alloy elements (for example, carbon, silicon, germanium, tin). Optionally, the crystallization step will be followed by a step of removing a residual amorphous or polycrystalline zone, for example made by anisotropic etching.
    [0016] According to one embodiment, the formation of the buffer layer protruding beyond the masking layer comprises, after the growth of the buffer layer from the substrate, a step of removing a portion of the masking layer from so as to discover said upper portion of the lateral flanks of the buffer layer.
    [0017] According to one embodiment, the growth of the buffer layer from the substrate is carried out so that the top of the buffer layer does not protrude beyond the masking layer before the step of removing a layer. part of the masking layer and protrudes beyond the masking layer after the step of removing a portion of the masking layer.
    [0018] According to one embodiment, the step of removing a portion of the masking layer is performed by etching. Prior to the step of removing a portion of the masking layer, a protective layer is formed on the upper face of the buffer layer and the etching of the masking layer causes the masking layer to be selectively the protective layer and the buffer layer. According to one embodiment, the protective layer is preserved during the formation of the epitaxial layer. According to one embodiment, the masking layer is formed of a single layer.
    [0019] According to one embodiment, the masking layer (200) is formed of a stack of layers. According to one embodiment, the masking layer comprises a stack of layers whose materials differ from one layer to another and are configured to be selectively removed from each other. According to one embodiment, the masking layer comprises a first layer forming a barrier layer surmounted by at least a second layer. The step of removing a portion of the masking layer is performed by etching the second layer and the etching of the second layer is performed with a stop on the first layer. According to one embodiment, the epitaxial growth of the buffer layer depends on the orientation of the crystalline planes of the substrate.
    [0020] According to one embodiment, the etching kinetics of the second layer is greater than at least twice the kinetics of etching of the first layer. Thus, the first layer forms a stop layer for etching the second layer. According to one embodiment, the step of removing a portion of the masking layer is performed by etching and the step of removing a portion of the masking layer is performed by controlling the etching time. According to one embodiment, the growth of the buffer layer from the substrate is continued until the buffer layer protrudes beyond the masking layer.
    [0021] According to one embodiment, the formation of a protective layer on said upper face of the buffer layer comprises: depositing a protective layer on the device; removing the entire protective layer on the lateral flanks of the buffer layer while retaining at least a portion of the protective layer on the masking layer and on said upper face of the buffer layer; removing the protective layer on the masking layer while leaving the protective layer on said upper face of the buffer layer.
    [0022] According to one embodiment, the buffer layer is made of a material identical to that of the epitaxial layer. According to one embodiment, the buffer layer is made of a material different from that of the epitaxial layer.
    [0023] According to one embodiment, the material of the buffer layer (300) and the material of the epitaxial layer have a mesh parameter mismatch of less than 2%. According to one embodiment, the buffer layer is made of a material different from that of the substrate. According to one embodiment, the material of the buffer layer and the material of the substrate have a mesh parameter mismatch of less than 10%. In one embodiment, an electrically insulative interfacial layer is deposited between the substrate and the masking layer. According to one embodiment, the substrate is made of silicon or an alloy of silicon and another material and the material of the buffer layer is a semiconductor material, preferably taken from: a germanium-silicon alloy (Si- Ge), gallium arsenide (GaAs), germanium (Ge), indium gallium arsenide (InGaAs), indium phosphide (InP), gallium nitride (GaN), nitride of aluminum (AIN) or an alloy of these materials. According to one embodiment, the substrate is made of silicon or an alloy of silicon and another material and the material of the epitaxial layer is a semiconductor material, preferably taken from: a germanium-silicon alloy (Si -Ge), gallium arsenide (GaAs), germanium (Ge), indium gallium arsenide (nGaAs), indium phosphide (InP), gallium nitride (GaN), nitride of aluminum (AIN) or an alloy of these materials. According to one embodiment, the materials of the buffer layer and of the epitaxial layer are chosen from the following combinations: a germanium-silicon (Si-Ge) alloy with silicon (Si), a germanium-silicon-alloy tin (Si-Ge-Sn) with germanium silicon (Si-Ge) alloy, gallium arsenide (GaAs) with germanium (Ge), indium gallium arsenide (InGaAs) with indium phosphide (InP), gallium nitride (GaN) with aluminum nitride (AlN). According to one embodiment, the width of each of the epitaxial layers formed on either side of the buffer layer is between 5 nm and 150 nm, the width being measured in a direction perpendicular to the lateral flanks.
    [0024] According to one embodiment, the masking layer electrically isolates the epitaxial layer of the substrate. According to one embodiment, the step of forming the epitaxial layer is reiterated so that the epitaxial layer is formed of a stack of layers having different or identical materials. Advantageously, this sequence makes it possible, for example, to obtain a channel and a buffer layer (interlayer layer between the channel and the gate insulator) in the same growth step. The trench has a depth at least equal to a value Hc such that Hc = KStan (0) where K is at least greater than 0.7, S is the trench width and 0 is the dislocation angle with respect to the plane of the trench. substrate. According to one embodiment, K is greater than 0.8 and preferably greater than or equal to 1. Advantageously K = 1. This makes it possible to effectively block the dislocations in the trench.
    [0025] When an upper layer is formed, preferably by growth, from a lower layer; Since said lower and upper layers do not have the same mesh parameter, the strong mesh parameter mismatch between the layers generates defects, more commonly referred to as interface dislocations. Deformation of the crystal mesh in the upper layer changes the inclination angle of the crystalline planes of said upper layer relative to the crystalline planes of the lower layer. By dislocation angle 0 is thus meant the angle of inclination of the crystalline planes of the upper layer relative to the lower layer. In general, the dislocation angle θ can be, for example, determined by transmission electron microscopy. The dislocation angle θ is advantageously between 30 ° and 90 °, and preferably between 50 ° and 60 °. According to one embodiment, the value Hc is between 0.5S and 2.5S, preferably between S and 2.5S. By preference, the value Hc is of the order of 2S.
    [0026] Advantageously, the aspect ratio is of the order of 2. According to a preferred embodiment, the trench has a depth greater than 2 times and preferably greater than 3 times the width of the trench.
    [0027] In a particularly advantageous manner, each epitaxial layer forms a channel of a transistor. Figures 2a to 2f detail the steps of the method of the invention according to a first embodiment. Figure 2a illustrates the formation of a masking layer 200 on a substrate 100. The manufacturing method is made from a substrate 100, a first material, preferably based on semiconductor. Advantageously, the section of the substrate 100, that is to say the orientation of the surface of this semiconductor crystal, depends on the intended application. According to non-limiting exemplary embodiments of the invention, it is possible to choose a substrate 100, preferably of silicon, whose crystal surface is oriented either in the <100> crystalline planes or in the <100> crystalline planes but off-axis. a few degrees, or in the crystalline planes <111>.
    [0028] The process begins with the formation of a masking layer 200 on the substrate 100. The masking layer 200 is preferably selected electrically insulating. According to a non-limiting embodiment, the masking layer 200 comprises a stack of layers 201, 202. Advantageously, the layers 201, 202 are formed from materials having different etch selectivities. The materials of the layers 201, 202 are preferably chosen so that it is possible to selectively etch a second layer 202 with respect to a first layer 201. According to an exemplary embodiment, the selectivity of the etching between these first and second layers. layers 201 and 202 may be 4 to 1, so that the first layer 201 is consumed 4 times more slowly than the second layer 202. Alternatively, the masking layer 200 is formed of a single layer. The thickness of the masking layer 200 (or the stack of layers 201, 202) is typically between 200 nanometers (nm) and 1 micron (pm = 10-6 meters). The thickness is measured in a direction perpendicular to the main surface of the substrate 100. The surface of the substrate 100 extends mainly in a plane parallel to the plane ZX of the orthogonal coordinate system illustrated in FIG. 2b. Thus, in the present patent application the thicknesses are generally taken in the direction Y perpendicular to the main face of the substrate on which the various layers rests. In the figures, the thickness is taken according to the vertical. According to an exemplary embodiment, an additional layer (not shown) is inserted between the substrate 100 and the masking layer 200 (or the first layer 201). This additional layer is configured so as to serve as a stop layer during a possible etching of the masking layer 200 (or the first layer 201) and thus to facilitate said etching, without causing damage to the substrate 100.
    [0029] FIG. 2b illustrates the formation of trenches 250 in the masking layer 200 (i.e., the stack of layers 201, 202) so as to reach the substrate 100. According to one embodiment, the trenches 250 are obtained by selectively etching the masking layer 200 (or the stack of layers 201, 202). The etching is preferably anisotropic. The etching is carried out so as to form trenches 250 whose walls, extending in a direction perpendicular to the surface of the substrate 100 (direction Y), comprise the lateral flanks of the masking layer 200 or the lateral flanks of the first and second layer 201, 202, according to the embodiment chosen. These trenches 250 have a shape ratio advantageously greater than 1. By form ratio is meant the ratio between the depth and the width of the trench 250. The depth of the trench 250 extends in a direction perpendicular to the surface of the trench. substrate 100. It is taken in the direction Y. The width of the trench 250 is the distance separating the opposite walls of the trench 250 and extends in a plane parallel to the surface of the substrate 100. It is taken in direction X Advantageously, the depth of the trench 250 corresponds to the thickness of the masking layer 200. The depth of the trench 250 is typically between 50 nm and 1 μm. The thickness of the trench 250 is preferably between 20 nm and 400 nm. In a particularly advantageous manner, the depth of the trench 250 is at least equal to the width of the trench 250.
    [0030] FIG. 2c illustrates the step of forming the buffer layer 300 in the trench 250 formed in the masking layer 200. Preferentially, the formation of the buffer layer 300 comprises an epitaxial growth of said buffer layer 300, starting from the substrate 100 By epitaxial growth is meant the formation of a crystalline layer of the same orientation in direct contact with the seed substrate 100. The formation may advantageously be in the form of a molecular beam growth ("MBE") for "molecular beam epitaxy" ) or in vapor phase ("CVD" for "chem ica I vapor deposition"). It could also be obtained by a succession of steps involving the deposition of an amorphous layer, its crystallization in contact with the seed susbtrate 100 and the removal of the undesirable deposited material. If the material of the buffer layer 300 has a mesh parameter different from that of the substrate 100 then it preferably has a crystal structure and a mesh parameter compatible with the crystalline properties of the surface of the substrate 100. As for the materials of the stack of layers 201, 202, they are advantageously compatible with the conditions of formation of the material of the buffer layer 300. According to an exemplary configuration, for the purpose of growing a silicon-germanium (SiGe) alloy for the buffer layer 300, a surface of the substrate 100 oriented along the crystalline planes <100> will preferably be used. In order to grow gallium arsenide (GaAs) for the buffer layer 300, a surface of the substrate 100 oriented along the <100> crystal planes, but slightly disoriented (at an angle of less than 10 degrees), will preferably be used. In another case, for growth of gallium nitride (GaN) for the buffer layer 300, a surface of the substrate 100 oriented along the <111> crystalline planes will preferably be used. Advantageously, the width of the trench 250 as well as the thickness of the masking layer 200 comprising, according to one embodiment, a first layer 201 and a second layer 202, are chosen so that the crystalline defects (ie the dislocations 50 observed in FIGS. 1 a to 1c) of the buffer layer 300, are confined to the lateral flanks of the first masking layer 201 without reaching the lateral flanks of the second insulating layer 202. According to non-limiting exemplary embodiments of the invention, the material of the masking layer 200 (or of the first layer 201) may be chosen from silicon oxide (SiO 2) or silicon nitride (Si 3 N 4) in the case where the buffer layer 300 comprises a material of the type such as gallium arsenide (GaAs), the silicon-germanium-tin alloy (SixGei_x_ySny, where x and y are the relative proportions of silicon and tin in the material, with x + y between 0 and 1) or indium phosphide (InP). In the case of growth of gallium nitride (GaN), it will be possible to use silicon nitride (Si3N4) as a material for the masking layer 200. At the end of the growth, the buffer layer 300 is partly confined in trench 250; its lateral edges being framed by the walls of the trench 250, its lower face being in contact with the substrate 100.
    [0031] According to the illustrated embodiment, the growth of the buffer layer is stopped before the height of the buffer layer (taken in the Y direction) exceeds the depth of the trench 250. The upper face of the buffer layer, representing the vertex of this layer 300 is not covered. The upper and lower faces of the buffer layer 300 extend in a plane substantially parallel to the surface of the substrate 100. FIG. 2d illustrates the formation of a protective layer 400 on at least the upper face of the buffer layer 300. According to a preferred but nonlimiting embodiment, the formation of the protective layer 400 is made in "full plate" that is to say on the entire surface. This step will preferably be followed by a partial removal of the protective layer 400 so as to leave in place the protective layer 400 only on the upper face of the buffer layer 300 as illustrated in Figure 2d. This partial removal includes, for example, planarization performed by chemical mechanical polishing. The protective layer 400 may be formed by a deposition technique or by a growth technique. According to another embodiment, the protective layer 400 is formed solely on the upper face of the buffer layer 300 by the use of photolithography and etching techniques, for example. The material of the protective layer 400 is advantageously chosen such that it can slow down or even block any epitaxial growth on the upper face of the buffer layer 300. Moreover, this material is also chosen so as to withstand the selective shrinkage of the second layer 202 (i.e., the upper layer of the stack of the masking layer 200). The material of the protective layer 400 is, for example, aluminum oxide (Al 2 O 3) in the case where the material of the buffer layer 300 is chosen from silicon oxide (SiO 2) or silicon nitride (Si3N4).
    [0032] Figure 2e illustrates the selective partial removal of the masking layer 200 that is the selective removal of the second masking layer 202. According to a particularly advantageous embodiment, the removal of the second layer 202 comprises an etching which may be isotropic or anisotropic and which may be carried out using an aqueous solution of hydrofluoric acid in the case where the layer 200 is produced. silicon dioxide (SiO2) and the layer 300 is a crystalline semiconductor so that the shrinkage takes place in a direction parallel to the lateral flanks of the buffer layer 300; said lateral flanks are therefore only weakly attacked during this step of removing the second insulating layer 202. In the case where the process would require the selective removal of the protective layer 400 relative to the insulating layers 200, 202: if the protective layer 400 comprises alumina (A1203) and the masking layers 200, 202 of the oxide of silicon (SiO2) and / or silicon nitride (Si3N4), then the etching solution could be formed from a mixture comprising sulfuric acid (H2504) and hydrogen peroxide (H2O2) or potassium hydroxide (KOH). In the case where the method requires the selective removal of the second masking layer 202 relative to the protective layer 400 and the first masking layer 201: if the second masking layer 202 comprises silicon nitride (Si3N4), the protective layer 400 of the alumina (A1203) and the first layer 201 of masking the silicon oxide (SiO2), then the etching solution could be formed from a mixture comprising trifluoromethane (CHF3) and the oxygen (02). In another case where the second insulating layer 202 comprises silicon oxide (SiO 2), the protective layer of alumina (Al 2 O 3) and the masking layer 201 of silicon nitride (Si 3 N 4), then the solution of etching of the masking layer 202 could be formed from hydrofluoric acid (HF). At the end of this selective partial removal of the masking layer 200, the buffer layer 300 advantageously protrudes beyond the masking layer 200. The buffer layer 300 thus exposes at least an upper portion of its lateral flanks. ; said lateral flanks extending in a plane orthogonal to the surface of the substrate 100 (thus in a plane YZ). Preferably, the height (measured along a direction Y orthogonal to the surface of the substrate) is from 5 to 150 nm of the portion of the buffer layer 300 protruding beyond the masking layer 200 corresponds to the thickness of the second masking layer 202 removed during the step of removing said layer. Advantageously, the first masking layer 201 acts as a stop layer during removal of the second masking layer 202. FIG. 2f illustrates the step of forming the epitaxial layer 500 on the lateral flanks of the buffer layer 300, flanks left uncovered during the previous step. Advantageously, the formation of the epitaxial layer 500 comprises a lateral growth made by molecular jet (acronym MBE in English) or in vapor phase (acronym CVD in English), in a direction perpendicular to the sides of the buffer layer 300 (thus in the direction X), of the epitaxial layer 500 from the lateral flanks of the buffer layer 300. According to one embodiment, the growth is epitaxial in the vapor phase (CVD type for "chemical vapor deposition" or "VPE" for "vapor phase epitaxy ", in English), or by molecular beam (MBE). In the case of a heteroepitaxy, the epitaxial layer 500 may be in mesh agreement or in mismatch, for example a mismatch of less than or equal to 1%, with the layer from which it was formed, That is, in this case, the buffer layer 300. Advantageously, the growth is monolayer by monolayer. In the case of heteroepitaxy, the mismatch or mismatch, that is to say the difference between the mesh parameters of the buffer layer 300 and those of the layer epitaxial 500, can cause defects in the structure of the latter if its thickness is such that the elastic energy it contains (due to its deformation) is greater than the energy for the creation of a crystalline defect. At first, the deposited atoms adapt to the crystalline structure of the buffer layer 300. However, as the thickness of the epitaxial layer 500 formed increases, the chemical properties of its elements outweigh those of the buffer layer. 300: the atoms choose the structure of the pure material, which could deform the crystal structure of the epitaxial layer 500 and cause the creation of dislocations 50. In order to avoid these inconveniences, the material of the epitaxial layer 500 advantageously has a crystalline structure , a mesh parameter and a thickness that make it suitable for growth without defects on the buffer layer 300. Following this epitaxial growth, the epitaxial layer 500 has a thickness, measured in a direction perpendicular to the sides of the buffer layer 300 ( therefore in the X direction), between 5 and 150 nm, preferably of the order of 10 nm.
    [0033] The epitaxial layer 500 is formed of a second material, preferably, which may be different from the first material of the substrate 100. According to nonlimiting examples, the materials of the buffer layer 300 and of the epitaxial layer 500 may be chosen from the following combinations (interchangeable), presenting materials whose mesh parameters are close: an alloy of germanium-silicon (Si-Ge) with silicon (Si), a silicon-germanium-tin alloy (Si-Ge-Sn) with silicon-germanium (SiGe), gallium arsenide (GaAs) with germanium (Ge), indium-gallium arsenide (InGaAs) with indium phosphide (InP), gallium nitride ( GaN) with aluminum nitride (AlN).
    [0034] Preferably, the material of the remaining masking layer 200, 201 is compatible with the selective growth of the material of the epitaxial layer 500 with respect to the material of the buffer layer 300. The material of the masking layer 200, 201 is advantageously shaped. so as to resist the chemical attacks implemented during the realization of the device. Advantageously, the embodiment described above does not depend on the lateral and vertical growth rate ratio of the buffer layer 300. The epitaxy of this buffer layer 300 is, in fact, entirely confined to the sides of a trench 250 formed in the masking layer 200. As indicated above, the crystalline defects are trapped in a lower part of the buffer layer 30, that is to say within a portion of the buffer layer which does not protrude at the However, an upper portion of the buffer layer 300, further away from the substrate 100 than the lower portion, will be free or substantially free of crystal defects and dislocations. This upper part extends, at least partly beyond the masking layer 200 and from the lower part. Since it is on the basis of this upper part that the epitaxial growth of the layer 500 is carried out, the latter is also free or practically free from crystalline defects and dislocations.
    [0035] Although the illustrated embodiment provides a masking layer 200 formed of two layers 201 and 202, a higher number of layers can be provided. Alternatively, we can provide a masking layer 200 formed of a single layer. In this case, stopping the etching of the masking layer 200 during partial removal to let the buffer layer 300 pass is achieved by controlling the etching time. FIGS. 3a to 3f illustrate another alternative of the method for producing the device according to the invention. This other approach is based on a particular growth of the buffer layer 300 in trenches 250 under conditions which make it possible to obtain a vertical growth rate (that is to say in a plane orthogonal to the surface of the substrate 100, therefore in the direction Y) greater than the lateral growth rate (that is to say in a plane parallel to the surface of the substrate 100, so in the direction X). Under these conditions, it is possible to grow a thickness (in a direction orthogonal to the surface of the substrate 100, so in the Y direction) of the buffer layer 300 greater than the depth (in a direction orthogonal to the surface of the substrate 100 , thus in the direction Y) of the trench 250, for example to present a fin type structure (in English "FIN"). FIG. 3a illustrates the formation of the masking layer 200 on the substrate 100. This masking layer 200 advantageously has the function of locating the formation of the buffer layer 300 as well as of confining the transverse crystalline defects of the buffer layer 300. FIG. 3b illustrates the formation of trenches 250 in the masking layer 200. The formation of the trenches 250 requires the use, for example, of photolithography and etching steps.
    [0036] The width of the trenches 250 is related to the thickness of the masking layer 200 in that the ratio of these two dimensions (i.e., the aspect ratio) must be sufficient to guarantee the confinement of the transverse crystalline defects. buffer layer 300 along the flanks of the masking layer 200. It has been observed that the growth of the germanium buffer layer 300 in the trenches 250 formed in the silicon oxide (SiO 2) masking layer 200 is achieved for aspect ratios greater than 1. Thus, the thickness (measured in the Y direction) of the masking layer 200 is at least equal to the width (measured along the X direction) of the trenches 250.
    [0037] Figure 3c illustrates the formation of buffer layer 300. Preferably, the formation of this layer comprises epitaxial growth (CVD, MBE) of said layer from substrate 100 anisotropically. In this case, the growth of the buffer layer 300 in a plane orthogonal to the surface of the substrate 100 is advantageously faster than the growth of said layer in a plane parallel to the surface of the substrate 100. Advantageously, growth anisotropy in a plane orthogonal to the surface of the substrate 100 makes it possible to guarantee the formation of the epitaxial layer in the form of a fin (in English "end"). In this embodiment, the substrate 100 is chosen such that the crystalline planes promote the formation (more precisely, the growth) of the buffer layer 300. In this particular embodiment, it is no longer necessary to using a stack of layers 201, 202 for the masking layer 200 because the growth of the buffer layer 300 is advantageously anisotropic; the horizontal growth in a plane parallel to the surface of the substrate 100 being dominant relative to the vertical growth (in a plane orthogonal to the surface of the substrate 100).
    [0038] The formation of the buffer layer 300 is performed so that the buffer layer 300 advantageously protrudes beyond the masking layer 200 leaving exposed at least its upper face, extending in a plane parallel to the surface of the substrate 100, and a portion of its lateral flanks; said lateral flanks extending in a plane orthogonal to the surface of the substrate 100. Advantageously, the height (measured in a direction orthogonal to the surface of the substrate) of the portion of the buffer layer 300 protruding beyond the layer of masking 200 is of the order of 10 to 200 nanometers and relates to the growth technique used to form the buffer layer 300. Figure 3d illustrates the formation of a protective layer 400 on at least the upper face of the layer buffer 300. The material of the protective layer 400 is preferably electrically insulating. Preferably, the formation of a protective layer 400 comprises a full-plate deposition followed by removal of the protective layer 400 selective with respect to the material of the buffer layer 300 and the material of the masking layer 200. can be done using the same means as those shown in Figure 2e. As a preference, the formation of the protective layer 400 must be non-uniform on the surface. In particular, the thickness of the protective layer 400 formed on the lateral flanks of the buffer layer 300 is less than the thickness of said layer on the upper face of the buffer layer and on the masking layer 200. As a preferred embodiment, the formation of the protective layer 400 is carried out by spraying. FIG. 3e illustrates the partial removal of the protective layer 400 so as to expose the lateral flanks of the buffer layer 300. Preferably, this partial shrinkage comprises etching, for example carried out using an aqueous solution of hydrofluoric acid. in the case of the removal of a layer 400 of silicon oxide. This etching is preferably performed in isotropic manner and limited in time so as to remove the entire thickness of the protective layer 400 on the flanks of the buffer layer 300 and to keep on the top of the latter. FIG. 3f illustrates the formation of the epitaxial layer 500 from the buffer layer 300. Advantageously, the epitaxial layer 500 is made from an epitaxial growth, laterally on the lateral flanks of the buffer layer 300; technique similar to that described in Figure 2f. According to non-limiting examples, the materials of the buffer layer 300 and of the epitaxial layer 500 may be chosen from the following combinations (interchangeable): an alloy of germanium-silicon (Si-Ge) with silicon (Si), from gallium arsenide (GaAs) with germanium (Ge), indium gallium arsenide (nGaAs) with indium phosphide (InP), gallium nitride (GaN) with aluminum nitride ( Aln). The materials of the buffer layer 300 and of the epitaxial layer 500 may be of identical crystalline structure but of different mesh parameters. In this case, the material of the epitaxial layer 500 will be constrained if its thickness is limited in order to avoid any elastic relaxation. The epitaxial layer 500 produced according to the method of the invention forms, for example, a channel whose width, extending in a direction orthogonal to the lateral flanks of the buffer layer 300, corresponds to the thickness of the epitaxial layer and whose depth corresponds to the height of the buffer layer 300 protruding beyond the masking layer 200, 201. Particularly advantageously, the channel is formed of a second material, preferably different from the first material of the substrate 100.
    [0039] According to a particular embodiment, the lateral growth of the epitaxial layer 500 may be followed by a lateral growth of a buffer layer 300 followed by another lateral growth of the epitaxial layer 500, so as to obtain several pairs of channels. epitaxial layer 500; preferably, the channels will be formed of different materials. The present invention advantageously makes it possible to produce layers of crystalline materials without dislocations 50 and for example channels constrained without dislocations. For constrained silicon channels, for example, silicon-germanium (SiGe) may be used for the buffer layer 300 to grow a silicon-based epitaxial layer 500 in voltage. In another example, to obtain constrained silicon channels, silicon carbide (SiC) for the buffer layer 300 may for example be used to grow an epitaxial layer 500 based on silicon in compression. According to another embodiment, to obtain silicon-germanium (SiGe) channels in compression, it will be possible to use, for the buffer layer 300, relaxed germanium. Advantageously, the material of the buffer layer 300 can be chosen with a large gap, that is to say a large bandgap (in other words preferably of the order of 1.5eV more than the gap of the material of the layer 500 ), so as to confine the conduction of the material of the epitaxial layer 500 without current flow in the material of the buffer layer 300. According to a preferred embodiment, the materials of the buffer layer 300 and the epitaxial layer 500 may be chosen so as to facilitate the production of contact electrodes.
    [0040] Figures 4a and 4b illustrate a preferred embodiment for forming a device comprises a FinFET type transistor, made from a layer formed according to the method of the invention. FinFET is the English acronym for "Fin-Shaped Field Effect Transistor", Fin being used here in connection with the shape that gives the architecture of these transistors to the drain and the source, which then resemble fins. This term designates transistors that are also called "3D transistors" which, unlike conventional transistors, develop in 3 dimensions. These transistors are composed of three elements: the drain, the source and the gate, with a channel that connects the source and the drain. FinFET etching of the transistors advantageously reduces by approximately 50% (depending on the process) the current leaks become problematic as the engraving of the processors is refined. Another advantage of FinFET transistors, they occupy a smaller surface since they are also built in height, which finally allows them to switch more quickly. To produce such FinFET transistors from the process according to the invention, after the formation of the epitaxial layer 500 from the upper part of the lateral flanks of the buffer layer 300, partial removal of said buffer layer 300 from the region in contact with the channels formed by the epitaxial layer 500, as shown in Figure 4a. The partial removal of the buffer layer may be achieved by etching, preferably anisotropic, of the buffer layer 300. Once the etching has been performed, a layer intended to form a grid 600 is deposited on a portion of the fins of the epitaxial layer 500. The gate 600 is advantageously configured so as to contact each of the fins of the epitaxial layer 500. According to another embodiment, a first grid (known as a "hairpiece" grid) is first made and subsequently removed. buffering layer 300 in a gate-last method. After the formation of the layer of the gate 300, on a portion of the fins of the epitaxial layer 500 not covered by the gate 300, contacts 525, 575 are made for forming sources and drain at the level of said epitaxial layer 500. as illustrated in Figure 4b.
    [0041] According to one embodiment, the buffer layer 300 may comprise a stop layer so that the withdrawal of the buffer layer 300 can be stopped by said stop layer. Preferably, the barrier layer comprises a material different from that used for the buffer layer 300. The protective layer 400 formed on the upper face of the buffer layer 300 to prevent a possible growth of the epitaxial layer 500 on the upper face, can be removed locally in order to form a bridging between the epitaxial zones of the epitaxial layer 500 formed on either side of the buffer layer 300. This may be advantageous for making a connection between two conductive fins or semiconductors separated by an electrically insulating buffer layer 300. The epitaxial layer 500 may comprise a stack of layers, for example, in the case of a type III-V epitaxial channel layer requiring an epitaxial capping layer before depositing the gate stack. . This embodiment makes it possible to remove the charge carriers traveling through the epitaxial layer 500 from the surface of the gate insulator, and also to preserve their mobility.
    [0042] Advantageously, a multitude of materials can be combined for the buffer layer 300 and the epitaxial layer 500 so as to offer different characteristics simultaneously on the same substrate 100. In particular, according to one embodiment, n-type and p-channel devices are produced on the same substrate 100. For example, the material of the epitaxial layer 500 may be chosen from silicon or indium gallium arsenide (InGaAs) (constrained or not) to form the n-type channel while the material of the buffer layer 300 may be be silicon-germanium (SiGe) (constrained or not) to form the n-type channel. According to another configuration example, by varying the silicon-germanium (SiGe) composition, devices are produced whose threshold voltage differs. The present invention also makes it possible to produce on the same substrate 100 different types of devices such as, for example, FinFET (field-effect transistor) type field effect transistors combined with transistors. laser type. In the case of the laser transistor, the specific architecture of such a transistor offers the possibility of obtaining germanium in voltage comprising a n-shaped doping shaped so as to produce a germanium-silicon laser transistor.
    [0043] As is clear from the foregoing description, the invention thus makes it possible to use the principle of confinement of dislocations 50 on a material other than that of the channel.
    [0044] In addition, the invention has the advantage of limiting the constraints imposed by the principle of confinement dislocations 50. The growth of the epitaxial layer 500 from the side flanks of the buffer layer 300 is advantageously not affected by the crystalline defects longitudinals developing in the buffer layer 300 during its formation from the substrate 100. On the other hand and particularly advantageously, the density of units or channels of the epitaxial layer 500 obtained from the method according to the invention is at less than twice the density of patterns that can be obtained by using photolithography steps. On the other hand, the width (in a plane parallel to the surface of the substrate 100) and the roughness of the hetero-epitaxial channels of the epitaxial layer 500 are determined solely by the growth of said layer. Advantageously, the hetero-epitaxial channels are formed in different materials from that of the substrate 100. The invention is not limited to the previously described embodiments and extends to all the embodiments covered by the claims.
    权利要求:
    Claims (33)
    [0001]
    REVENDICATIONS1. A method of producing a crystalline layer from a crystalline substrate (100) of a first material on which a masking layer (200) has previously been deposited; said masking layer (200) comprising at least one trench (250) forming an access to the substrate (100), characterized in that the trench (250) has a depth at least equal to a value Hc such that Hc = KStan ( 0) where K is at least greater than 0.7, S is the width of the trench (250) and 0 is the angle of the dislocations relative to the plane of the substrate (100) and in that the method comprises the following steps: - formation a crystalline buffer layer (300) located at least in part in the trench (250) of the masking layer (200), extending from the substrate (100) and protruding beyond the masking layer ( 200) so that an upper portion of the lateral flanks of said buffer layer (300) is left uncovered, the forming step comprising growing the buffer layer (300) from the crystalline substrate (100) of to give the buffer layer (300) a crystal structure using the structure e crystalline crystalline substrate (100), - forming a crystalline epitaxial layer (500) in a second material, different from the material of the buffer layer (300), by growing from said upper part of the lateral flanks of the layer buffer (300) left uncovered.
    [0002]
    2. Method according to the preceding claim wherein the growth of the buffer layer (300) comprises an epitaxial growth from the substrate (100).
    [0003]
    3. The method of claim 1 wherein the growth of the buffer layer (300) comprises a deposition of said layer (300), followed by crystallization annealing.
    [0004]
    A method according to any one of the preceding claims wherein the masking layer (200), in particular its material and structure, is selected to prevent growth of the epitaxial layer (500) from the masking (200).
    [0005]
    A method according to any preceding claim wherein the formation of the buffer layer (300) is performed so as to leave exposed an upper face of the buffer layer (300) in addition to said upper portion of the lateral flanks of the buffer layer (300) and in which, prior to the formation of the epitaxial layer (500), a protective layer (400) is formed on said upper face of the buffer layer (300) so as to reveal only said upper portion of the lateral flanks of the buffer layer (300) left uncovered.
    [0006]
    6. Method according to the preceding claim wherein the protective layer (400), in particular its material and its structure, is chosen so as to prevent the growth of the epitaxial layer (500) from the protective layer (400). .
    [0007]
    The method of any one of the preceding claims wherein the formation of the epitaxial layer (500) comprises epitaxially growing from the top of the side flanks of the buffer layer (300) left uncovered.
    [0008]
    8. The method according to the preceding claim wherein the formation of the epitaxial layer (500) comprises an anisotropic growth directed perpendicular to the lateral flanks of the buffer layer (300) left exposed.
    [0009]
    9. Process according to any one of claims 1 to 6 wherein the formation of the epitaxial layer (500) comprises a deposit of amorphous material followed by a crystallization annealing step of said material.
    [0010]
    The method of any of the preceding claims wherein forming the buffer layer (300) protruding beyond the masking layer (200) comprises, after growing the buffer layer (300) from the substrate (100), a step of removing a portion of the masking layer (200) so as to expose said upper portion of the side flanks of the buffer layer (300).
    [0011]
    11. Method according to the preceding claim wherein the growth of the buffer layer (300) from the substrate (100) is carried out so that the top of the buffer layer (300) does not protrude beyond the masking layer (200) before the step of removing a portion of the masking layer (200) and protruding beyond the masking layer (200) after the step of removing a portion of the masking layer (200); masking layer (200).
    [0012]
    12. Method according to any one of the two preceding claims wherein the step of removing a portion of the masking layer (200) is performed by etching, in which prior to the step of removing a portion of the masking layer (200) forms a protective layer (400) on the upper side of the buffer layer (300) and wherein the etching of the masking layer (200) etches the masking layer ( 200) selectively to the protection layer (400) and the buffer layer (300).
    [0013]
    13. Method according to the preceding claim wherein the protective layer (400) is preserved during the formation of the epitaxial layer (500).
    [0014]
    The method of any of the preceding claims wherein the masking layer (200) is formed of a single layer.
    [0015]
    15. Method according to any one of claims 1 to 13 wherein the masking layer (200) is formed of a stack of layers (201, 202).
    [0016]
    16. The method according to the preceding claim wherein the masking layer (200) comprises a stack of layers (201, 202) whose materials differ from one layer to another and are configured so as to be selectively removed by compared to others.
    [0017]
    17. A method according to any one of the two preceding claims taken in combination with any one of claims 10 to 13, wherein the masking layer (200) comprises a first layer (201) forming a surmounted barrier layer. at least one second layer (202), wherein the step of removing a portion of the masking layer (200) is performed by etching the second layer (202) and wherein etching the second layer ( 202) is stopped with the first layer (201).
    [0018]
    18. A method according to any one of claims 10 to 13 wherein the step of removing a portion of the masking layer (200) is performed by etching and wherein the step of removing a portion of the masking layer (200) is performed by controlling the etching time.
    [0019]
    The method of any one of claims 1 to 10 wherein the growth of the buffer layer (300) from the substrate (100) is continued until the buffer layer (300) protrudes beyond the masking layer (200).
    [0020]
    20. Method according to the preceding claim taken in combination with any one of claims 5 or 6 wherein the formation of a protective layer (400) on said upper face of the buffer layer (300) comprises: - the deposit a protective layer (400) on the device - removing the entire protective layer (400) on the lateral flanks of the buffer layer (300) while retaining at least a portion of the protective layer (400) on the masking layer (200) and on said upper side of the buffer layer (300); - removing the protective layer (400) on the masking layer (200) leaving in place the protective layer (400) on said upper face of the buffer layer (300).
    [0021]
    The method of any of the preceding claims wherein the buffer layer (300) is made of a material identical to that of the epitaxial layer (500).
    [0022]
    The method of any one of claims 1 to 20 wherein the buffer layer (300) is made of a material different from that of the epitaxial layer (500).
    [0023]
    23. Method according to the preceding claim wherein the material of the buffer layer (300) and the material of the epitaxial layer (500) have a mismatch of less than 2% mesh.
    [0024]
    24. The method as claimed in claim 1, in which K is greater than 0.8 and preferably greater than or equal to 1.
    [0025]
    25. The method of any one of the preceding claims wherein K = 1.
    [0026]
    The method of any of the preceding claims wherein the buffer layer (300) is made of a material different from that of the substrate (100).
    [0027]
    27. Method according to the preceding claim wherein the material of the buffer layer (300) and the substrate material (100) have a mismatch of less than 10% mesh.
    [0028]
    The method of any one of the preceding claims wherein an electrically insulating interfacial layer is deposited between the substrate (100) and the masking layer (200).
    [0029]
    The method of any of the preceding claims wherein the materials of the buffer layer (300) and the epitaxial layer (500) are selected from the following combinations: a germanium-silicon (Si-Ge) alloy with silicon (Si), an alloy of germanium-silicon-tin (Si-Ge-Sn) with silicon-germanium alloy (Si-Ge), gallium arsenide (GaAs) with germanium (Ge), indium gallium arsenide (InGaAs) with indium phosphide (InP), gallium nitride (GaN) with aluminum nitride (AlN).
    [0030]
    The method of any of the preceding claims wherein the masking layer (200) electrically isolates the epitaxial layer (500) from the substrate (100).
    [0031]
    31. The method as claimed in any one of the preceding claims, wherein the step of forming the epitaxial layer (500) is repeated so that the epitaxial layer (500) is formed of a stack of layers having different materials. or the same.
    [0032]
    32. A microelectronic device comprising a crystalline substrate (100) covered with a masking layer (200) comprising at least one trench (250) forming an access to the substrate (100), the trench (250) having a depth at least equal to a value Hc such that Hc = KStan (0) where K is at least greater than 0.7, S is the width of the trench (250) and 0 is the angle of the dislocations relative to the plane of the substrate (100), characterized in that it comprises: a crystalline buffer layer (300) formed at least in part in the trench (250) and extending from the substrate (100) to protrude from the masking layer (200), a crystalline epitaxial layer (500) formed at least on a portion of the side flanks of the buffer layer (300) which protrudes beyond the masking layer (200).
    [0033]
    33. Device according to the preceding claim wherein each epitaxial layer (500) forms a channel of a transistor.
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    公开号 | 公开日
    FR3023058B1|2017-09-29|
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    EP2963674A1|2016-01-06|
    US20150380491A1|2015-12-31|
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1456201A|FR3023058B1|2014-06-30|2014-06-30|METHOD FOR PRODUCING A MICROELECTRONIC DEVICE|FR1456201A| FR3023058B1|2014-06-30|2014-06-30|METHOD FOR PRODUCING A MICROELECTRONIC DEVICE|
    EP15174396.0A| EP2963674A1|2014-06-30|2015-06-29|Method for producing a microelectronic device|
    US14/753,662| US9917153B2|2014-06-30|2015-06-29|Method for producing a microelectronic device|
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